1. Field of the Invention
The present invention relates generally to pipelined analog-to-digital converters.
2. Description of the Related Art
An impressive variety of modern electronic systems (e.g., scanners, camcorders, communication modems, medical image processors and high-definition television) require the signal conditioning provided by analog-to-digital converters (ADCs) which convert input data signals to digital codes with a resolution that corresponds to the number of bits in the digital code.
An especially useful ADC structure is exemplified in FIG. 1 which illustrates a pipelined ADC system 20 that includes a sampler 22 and N pipelined converter stages 24. The sampler provides samples of an input data signal Sin and each pipelined converter stage converts a respective analog input data signal to that converter stage""s predetermined number of digital bits and passes an amplified residue signal to a succeeding converter stage (the amplified residue signal is the respective analog input signal of the succeeding converter stage).
As the succeeding converter stage converts its received residue signal in a similar manner, the preceding converter stage is converting a succeeding analog input signal. All converter stages, therefore, are simultaneously converting input data signals to their respective digital bits with final converted words issuing at the same rate as the sampling rate of input data signals. By partitioning the conversion among a number of low resolution converter stages, the pipelined structure provides high resolution a high sampling speeds.
Broken lines 26 in FIG. 1 indicate that the ith converter stage, for example, comprises an mi-bit ADC 30 which provides digital bits Di and also comprises an mi-bit digital-to-analog converter (DAC) 32 that converts mi bits to an analog signal which is then subtracted in a summer 34 from this converter stage""s respective analog input to form an analog residue Ri that is amplified in a respective amplifier 36 with a respective gain Gi and passed to a successive converter stage.
The N converter stages thus generate digital bits D1, D2-DN that correspond to each input data signal. Generally, one or more redundant bits are also generated and a control and correction logic 37 includes circuits (e.g., full adders) that use the bits of succeeding stages to digitally correct preceding-stage errors which result from various degrading effects. The control and correction logic also includes circuits (e.g., shift registers) that time-align the corresponding digital bits of the different converter stages to produce the final digital code Cdgtl.
A particularly useful structure for realizing the converter stage structure within the broken line 38 is a switched-capacitor multiplying digital-to-analog converter (MDAC) 40 which is indicated by the broken-line arrow 39. The MDAC 40 is shown in a 1.5 bit version which comprises a differential amplifier 42, equal-sized capacitors C1 and C2 and a plurality of switches. For clarity of illustration, the switches are not shown but in operation, the switches are placed in first and second states which configure the MDAC 40 (in states 40A and 40B) for first and second operational phases.
In the first operational phase that corresponds to state 40A, both capacitors are coupled to their converter stage""s input voltage vin. Because the amplifier 42 has high gain, its inverting and noninverting inputs are at substantially the same potential, i.e., they are both at ground potential. Accordingly, the capacitors take on an electrical charge that corresponds to the input voltage vin.
In the second operational phase that corresponds to state 40A, a decision signal DVr is applied (by the mi-bit ADC 30) to one plate of the capacitor C1 which transfers its electrical charge to the capacitor C2 as indicated by charge-transfer arrow 44. The voltage Vr represents plus and minus limits of the input range of the converter stage. D is set by the decision of the corresponding ADC converter stage concerning its analog input signal and, for a 1.5 bit converter stage, takes on values +1, 0 and xe2x88x921. Because the capacitors C1 and C2 have the same capacitance, the amplifier""s output voltage vout is doubled by the charge transfer and, when D is +1 and xe2x88x921, is also offset respectively up and down. The proper gained-up residue signal is thereby provided to the succeeding converter stage.
An error component will be inserted in the gained up residue signal if the capacitances of the capacitors C1 and C2 differ, i.e., if they are not matched. An error component will also be inserted if the gain A of the amplifier 40 is not infinite. As indicated in FIG. 1, the voltage at the inverting input of the amplifier is xe2x88x92vout/A. This is an error voltage that appears at one plate of the capacitor C1 and corrupts the transfer of electrical charge to the capacitor C2 which, in turn, introduces error into the gained up residue signal. These converter stage errors introduce a nonlinearity into the output digital code Cdgtl of the pipelined ADC 20 which cannot be removed by the control and correction logic 37.
Fortunately, current fabrication technologies can sufficiently match the capacitors to achieve conversion accuracies in excess of 12 bits. It is quite difficult, however, to realize a large amplifier gain A at the exceedingly high frequencies (e.g., 1 GHz) required of modern pipelined ADCs. Although various modifications have been proposed to reduce the conversion errors introduced by insufficient differential amplifier gain, they are generally complex and/or add substantial structure and cost to pipelined ADC systems.
The present invention is directed to methods and structures for interleavably processing data signals and error signals in alternating first and second operational phases of successive converter stages of pipelined analog-to-digital converter systems
These goals are realized with converter stages that are arranged to interleavably process data signals and error signals in alternating first and second operational phases as they convert input data signals to corresponding digital code.
The interleaved methods and structures significantly reduce conversion errors caused by less-than-infinite and/or nonlinear gain A of converter stage amplifiers and/or samplers. Because this performance enhancement is realized primarily with existing pipelined structure, modification complexity and cost of conventional pipelined systems is substantially reduced. The advantages of the invention are also realized with minimal increase in power consumption and circuit space.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.